To understand the timing a bit more I programmed an ESP8266 to give me a controllable RST and GPIO pulse generator to test the effect on another module. I discovered some things that may be useful if anybody is driving the reset line or setting into program mode.
1) As described in the link the reset pulse was coupled into CH_PD rather than RST to make it work for all modules. This wasn't really explained there. I have found that on the ESP-12F modules I use, the RST line seems to be pulled high via a 12K resistor but also tied to ground through a 470R and 1uF capacitor in series. This maybe to give a delayed reset on power up. However, this does have consequences on driving it logically rather than via a reset switch. Using a capacitively coupled pulse would need a high value capacitor to overcome the 1uF. Any drive should either have an impedance low with respect to 470R or a pulse width long enough to discharge the 1uF capacitor.
2) The minimum pulse width for reset seems to be around 300uSec. This applies to both the RST line and the CH_PD line
3) The GPIO0 line must be maintained low for some considerable time after the reset in order to enter PROG mode. I found this to be about 17mSec. I needed to make my capacitively coupled GPIO circuit have a pulse width greater than this.
An example trace when driving the RST line through a 220R is shown here.
The initial step is the effect of the internal 470R resistor and then the capacitor starts to discharge.