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Re: ESP8266 12E/F I/O interfacing

PostPosted: Wed Jan 17, 2018 11:59 am
by Erik84750
btidey wrote:Few comments

MOSFET seems to be upside down. Drain is shown connected to 0V. I suspect you are trying for an open drain output.

There is nothing limiting input current to opto. If you are assuming external resistor or a current source that's ok but I would put in at least a limiting series resistor to avoid blowing the opto.

The output would follow the input when used in input mode. That may be OK.

If the GPIO is output and the input turns the opto on then there is a serious conflict. You should have a series resistor from the emitter to limit this. A value of say 2.2K will still allow a good high to be developed on input but limit the current if the opto turns on and GPIO is output low.

Schematic attached for your review, thanks and greetings

Re: ESP8266 12E/F I/O interfacing

PostPosted: Wed Jan 17, 2018 2:28 pm
by Erik84750
Erik84750 wrote:
btidey wrote:Few comments

MOSFET seems to be upside down. Drain is shown connected to 0V. I suspect you are trying for an open drain output.

There is nothing limiting input current to opto. If you are assuming external resistor or a current source that's ok but I would put in at least a limiting series resistor to avoid blowing the opto.

The output would follow the input when used in input mode. That may be OK.

If the GPIO is output and the input turns the opto on then there is a serious conflict. You should have a series resistor from the emitter to limit this. A value of say 2.2K will still allow a good high to be developed on input but limit the current if the opto turns on and GPIO is output low.

Schematic attached for your review, thanks and greetings


And here are the gerber files in case you want to fabricate it.

Re: ESP8266 12E/F I/O interfacing

PostPosted: Wed Jan 17, 2018 4:25 pm
by btidey
That looks better.