ESP8266 Community Forum

Well friends, after a good time of research and study of the nosdk8266 project, I have come to the simple conclusion that it is not worth playing with the PLL dividers, so I thought, what if we turn it off? The base PLL runs at 1040MHz, in the nosdk8266 project it reached 346MHz of processor frequency, but if we turn off the PLL divider and overclock even more the processor itself, could we reach 1040MHz of processor and PLL at the same time?

Very little chance, but be my guest

When a PLL is in bypass, the PLL clock logic is kept in reset. ... The bypass controls are used by software to change the source clock input reference (for Peripheral and SDRAM PLLs) and is recommended when changing settings that may affect the ability of the VCO to maintain lock. regards Yash