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Re: Memory Layout

PostPosted: Sat Sep 06, 2014 3:12 am
by Bert
Squonk wrote:[...]
No, the AT parser is not there, or we should see the AT command strings, which is not the case.

Which was exactly the point I was trying to make ;)

Re: Memory Layout

PostPosted: Sat Sep 06, 2014 3:14 am
by Bert
Squonk wrote:Yes, but it looks like I-RAM is a kind of I-ROM mirror or cache, or at least a R/W copy of I-ROM.

106Micro is a cacheless architecture, so it's definitely not a cache. It could still be a mirror (or shadow if you wish), but it may have been modified since the shadowing took place.

Re: Memory Layout

PostPosted: Sat Sep 06, 2014 3:37 am
by Squonk
Bert wrote:
Squonk wrote:Yes, but it looks like I-RAM is a kind of I-ROM mirror or cache, or at least a R/W copy of I-ROM.

106Micro is a cacheless architecture, so it's definitely not a cache. It could still be a mirror (or shadow if you wish), but it may have been modified since the shadowing took place.

Agreed, this may be convenient to patch exception vectors, for example.

Looking at the dump in parallel to the ordered symbols from the "eagle_rom_addr.v6.ld" file (see corresponding spreadsheet attached), you can observe that for the corresponding addresses, it looks like most of the time there is some kind of pattern, "00", "00 00" or "fc 00", as if it the last instruction from the previous routine is padded to long word boundary. I haven't check all symbols, but for the 50 first ones and some random other ones, this pattern is not a simple coincidence.

However, there are some cases where this pattern is offset by +/- 1 long word, so I just hope that there are not as many ROM contents as there are PCB layouts (and cookies recipes :P )

Re: Memory Layout

PostPosted: Sat Sep 06, 2014 3:43 am
by Squonk
I tried disassembling the raw dump file with
Code: Select allxt-objdump -b binary -mxtensa -D esp8266.bin
from the VM, but all I get is an exception :(