Discuss here different C compiler set ups, and compiling executables for the ESP8266

User avatar
By Zachary Comstock
#53176 Regarding "reset halt": I have found the following:

An ultra-low-power configuration may not have a PIF, but still require some method of
initializing the local memories. One method of initializing a processor would be to have a
master processor program the ultra-low-power processor’s local memories through the
OCD interface. This method involves very few wires to initialize a processor’s memories.
Figure 51 shows a system with a master processor and a slave processor. The master
asserts the OCDHaltOnReset port of the slave processor, before the slave processor
comes out reset. Once the reset is removed, the slave processor enters inter OCD
mode and await instructions from the OCD port, which is driven by a IEEE-compliant
TAP controller. The master processor controls the slave processor TAP through the five
JTAG pins, and issues instructions to write the slave processor’s local memories. The
master can use TIE export states to control the slave, or traditional memory mapped
GPIO as well.


(Xtensa System Designer’s Guide found on some chinese website)

So there is a port named OCDHaltOnReset and we don't know if it's connected in the RTL anywhere
User avatar
By Santos07
#92949 Hi,

Trying to connect to my ESP8266 devkit using ESP-PROG I get the following error:

```
openocd -f tcl/interface/ftdi/esp32_devkitj_v1.cfg -f tcl/target/esp8266.cfg
Open On-Chip Debugger 0.9.0-rc1-dev-00457-g6a7dd376 (2021-11-30-15:27)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
none separate
adapter speed: 20000 kHz
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
adapter speed: 1000 kHz
stop_wdt
Info : clock speed 1000 kHz
Error: JTAG scan chain interrogation failed: all zeroes
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway...
Error: esp8266.cpu: IR capture error; saw 0x00 not 0x01
Warn : Bypassing JTAG setup events due to errors
Warn : Warning: Target not halted, breakpoint/watchpoint state may be unpredictable.
```

`all zeroes` suggests wiring issues. But my wiring seems to be OK

This is my wiring:
TMS -> GPIO 14
TDI -> GPIO 12
TCK -> GPIO 13
TDO -> GPIO 15
RST -> RST

Any ideas on how to troubleshoot this?
Thanks