ESP8266 Community Forum

jcmvbkbc wrote:So, reporting gcc status:

- no support for call0 ABI in current gcc;
- nobody in Cadence is currently working on implementing it;
- whether that support could be implemented by Cadence is discussed, my estimation that the answer would be positive is low.

Please insist in that it is a once in a lifetime opportunity for Cadence to have its XTensa architecture to reach the public!

Squonk wrote:Please insist in that it is a once in a lifetime opportunity for Cadence to have its XTensa architecture to reach the public!

Agreed. If they still don't want to, is there a way they can release some docs disclosing the specifics of the CALL0 abi?

Yes, although I suspect implementing this into GCC is non trivial...

But I really mean it: if they want the XTensa architecture to stand out and compete with ARM or MIPS core, this is the way to do it, now!

EDIT: actually, the XTensa GCC compiler in the VM is (somewhat) working, so if they can point us on one that was supposed to work, not necessarily the latest GCC.

Squonk wrote:

jcmvbkbc wrote:So, reporting gcc status:

- no support for call0 ABI in current gcc;
- nobody in Cadence is currently working on implementing it;
- whether that support could be implemented by Cadence is discussed, my estimation that the answer would be positive is low.

Please insist in that it is a once in a lifetime opportunity for Cadence to have its XTensa architecture to reach the public!

Espressif is talking with Cadence, they just met last week about this. I am in direct contact with CEO of Espressif. (he called me )

Richard.