- Fri Mar 24, 2017 2:59 pm
synfinatic wrote:So I can't loose interrupts. I need perfect accuracy or there's really no point. It needs to be on CHANGE unless I were to do something strange and connect each encoder channel to two ESP pins and distribute the interrupts across 8 pins instead of 4 (each pin waits on Rising or Falling).
Sorry, but you are wrong here. If you need an interrupt on both edges (falling and rising) you do not need TWO inputs to realize this. You just reconfigure (reattach in this case) the interrupt in the ISR to wait an opposite edge when you detect one.
I still do not get why you need two interrupts per encoder. There are several encoder types, but let's say simple general encoder has two channels A and B and the edges on these channels allow to determine rotation direction. Clockwise - A channel leads and B channel follows; anticlockwise - B channel leads and A channel follows. Suppose A channel is on interrupt; when it fires, you read B channel and have full info about the situation - if B is low, it is rotated clockwise and vise versa.
This chis does not supports interrupt priorities so if several events occur at the same time - of course some could be lost. There is only one flag (in the dedicated register) for every interrupt, so you can serve the last interrupt on the particular pin, despite the fact that several events occurred during your busy (e.g. serving other interrupt) time.
I would suggest to keep this cpu for communications only and for your main program go for arm - e.g. stm32F4xx family. These chips are superior in every way.