A place users can post their projects. If you have a small project and would like your own dedicated place to post and have others chat about it then this is your spot.

User avatar
By davydnorris
btidey wrote:As has been mentioned in another thread there is also the interesting field called I2S_I2S_TX_DATA_NUM in the FIFO control register which can take values from 0 - 63.

I don't do anything with this at the moment and its purpose doesn't seem to be known or if it is relevant in dma mode. I'll try a few experiments to see if I can figure out what effect it has.

I think I can help with that one - in FIFO mode, this is the number of samples to transmit via the FIFO. Once you start the system it will transmit this number of samples. Whatever gets put on the FIFO will be transmitted, but if you put nothing on it then it'll transmit DATA_NUM samples of 0. If you put one value then it will be transmitted DATA_NUM times. If you put a bunch of values and stop before the end of the count then it'll keep transmitting the last value until it's done DATA_NUM.

I think the corresponding register for the receive side is I2SRXEOF_NUM

FIFO mode is most useful for displays and the like where you transmit data sporadically. DMA mode is best for continuous transmission.

**EDIT** Just looked in the i2s_reg.h file and it looks like there both TX and RX DATA_NUM register areas, so RXEOF_NUM isn't the same thing. Since it's set to the DMA buffer size when you're using DMA mode, I'm guessing it's used to count how many samples to transfer before flipping to the next buffer area, but now I'm not so sure.
User avatar
By btidey
#89643 Thanks for info; so maybe not useful for trying to get 32 bit sample operation.

I think dma buffer flipping is done using the datalen field in slc_queue_item.
User avatar
By davydnorris
#89650 It's a weird one - I2SRXEOF_NUM has a register area and an entire word all to itself. The ESP Technical Reference says:

Register I2SRXEOF_NUM sets the number of data to be received when the Rx FIFO triggers the SLC transport (unit: 4 bytes).

So my reading on this is that maybe that's the number of words transferred from the FIFO to the buffer in a single DMA transfer, which would be why the examples set it to the same size as the buffer area. That would mean it shouldn't ever be set larger than the size of the FIFO which is 128 words, but the value isn't bit map protected:

Code: Select all#define I2SRXEOF_NUM (DR_REG_I2S_BASE + 0x0024)
#define I2S_I2S_RX_EOF_NUM_S 0
User avatar
By btidey
#89657 Could be that the slc dma trigger operation is different for output and input. E.g. the I2SRXEOF_NUM is used for input and the datalen used for output.

It is also somewhat curious that there is both a datalen and a blocksize in the slc queue item. For output I just make these the same but maybe the datalen reflects how much data has been input.

As has been noted by many others the espressif documentation doesn't help too much in this area.