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Re: espI2sClockgen

PostPosted: Thu Nov 26, 2020 4:46 am
by btidey
Word length control bits are a bit nasty having only 4 bits with a base of 16 so my understanding is same as yours that maximum sample size is 31 bits.

However, i2s devices normally just obey the word clock and either truncate or fill to suit.

I think the best combination to get close to 48KHz sampling from the 160MHz internal clock is to use a total pre-scale of 16 to give a 2.5Mz bit clock (say div1=4,div2=4) and then a word length of 26 bits. This gives 48.077Khz , about 0.16% high. So a recording would play back slightly slow on a real 48KHz device by about 6 seconds per hour.

Re: espI2sClockgen

PostPosted: Thu Nov 26, 2020 11:06 am
by btidey
I have enhanced the clock search criteria to allow finding matches with specific I2S word lengths.

This can either be a single number e.g. 24 or a range like 24,31

Re: espI2sClockgen

PostPosted: Thu Nov 26, 2020 9:24 pm
by davydnorris
Thanks for that - at the moment I have been assuming that all bits on will give me 32 but was still unsure, and that gives me the same rate as you if I use 4 and 13 as my scaler values.

I'll definitely try your settings as well - if it is truly only 31 bits then my values are out, but from the documentation on my I2S device, I am confused as to whether the bits even have an effect on the rate, and that all they do is affect the word clock. My I2S device data sheet says there must be 64 SCK cycles in each WS stereo frame (despite it being a 24 bit mic), which I think means I have to set my bits to 32 and my bit clock will need to be based on this.

I don't suppose you've done a trace of your bit/word clock to see what the behaviour is?

Also I remember seeing in documentation that there were minimum values for the divider and prescaler:

Code: Select allCLK_I2S = 160MHz / I2S_CLKM_DIV_NUM
      WS = BCLK/ 2 / (16 + I2S_BITS_MOD)
      Note that I2S_CLKM_DIV_NUM must be >5 for I2S data
      I2S_CLKM_DIV_NUM - 5-127
      I2S_BCK_DIV_NUM - 2-127

Have you found this?

Re: espI2sClockgen

PostPosted: Fri Nov 27, 2020 8:14 am
by btidey
I have not had a problem using BDM 1->63 and CDM 2->63 but this is I2S output mode. My search is constrained to those values. I don't know if it is different for input but I wouldn't have thought so. The 127 I think was a mistake in the docs. These are 6 bit fields.

Up till now I had been focused on the bit clock and the data out not worrying about the word select signal as it didn't affect what I was doing. I'll have a look at playing around with I2S_BITS_MOD and seeing effect on word select signal. It would certainly be interesting if one could do 32 bits which would allow the 4/13 scaling.