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Re: Exploring the SPI Master interface

PostPosted: Wed Apr 08, 2015 10:35 am
by metalphreak
Thanks for posting up the info you've got so far. It helped me get started with the SPI Clock settings and I think I've worked it out.

My full post is at http://d.av.id.au/blog/hardware-spi-clock-registers/

It is the difference between SPI_CLKCNT_H and SPI_CLKCNT_L that sets the duty cycle of the SPI clock. If _H is higher than _L, then the difference is the number of clock cycles the SPI clock out is high. If _H is lower than _L, it is the number of clock cycles the SPI clock out is low. (No matter what, the normal high first than low second transition remains).

If you had:
SPI_CLKCNT_N set to 0x09 (for 10 cycles)
SPI_CLKCNT_H set to 0x09
SPI_CLKCNT_L set to 0x03

Then the SPI clock out would be high for 6 cycles and low for 4 cycles. The actual offset from 0 for _H and _L doesn't matter, as long as both are equal to or less than SPI_CLKCNT_N.

SPI_CLKCNT_N set to 0x09 (for 10 cycles)
SPI_CLKCNT_H set to 0x06
SPI_CLKCNT_L set to 0x00

This would give the exact same results.

To get 80MHz sys clock, you need to set bit31 (SPI_CLK_EQU_SYSCLK) and also when you setup PERIPHS_IO_MUX make sure bit9 is set, otherwise it won't work.

Code: Select allvoid spi_debug_init(uint8 spi_no)
{
   uint32 regvalue;
   if(spi_no>1)       return; //handle invalid input number
   //bit9 of PERIPHS_IO_MUX should be cleared when HSPI clock doesn't equal CPU clock
   //bit8 of PERIPHS_IO_MUX should be cleared when SPI clock doesn't equal CPU clock
   if(spi_no==SPI){
      WRITE_PERI_REG(PERIPHS_IO_MUX, 0x005); //clear bit9,and bit8
      PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, 1);//configure io to spi mode
      PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 1);//configure io to spi mode   
      PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, 1);//configure io to spi mode   
      PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, 1);//configure io to spi mode   
   }else if(spi_no==HSPI){
      WRITE_PERI_REG(PERIPHS_IO_MUX, 0x305); //set bit9
      PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2);//configure io to spi mode
      PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2);//configure io to spi mode   
      PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2);//configure io to spi mode   
      PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, 2);//configure io to spi mode   
   }         

   SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_CS_SETUP|SPI_CS_HOLD|SPI_USR_COMMAND);
   CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_FLASH_MODE|SPI_WR_BYTE_ORDER);

   WRITE_PERI_REG(SPI_CLOCK(spi_no), SPI_CLK_EQU_SYSCLK);

Re: Exploring the SPI Master interface

PostPosted: Wed Jun 29, 2016 6:17 pm
by Egzon Mulaj
Note: GPIO15 needs to be tied to GND when booting from the onboard SPI flash (see below table). Just use a suitable pull down resistor (4.7k or something) so the pin can still properly function as a chip select. Do not connect it directly to GND!


LINK http://d.av.id.au/blog/esp8266-hardware ... nd-pinout/

Re: Exploring the SPI Master interface

PostPosted: Thu Aug 04, 2016 11:55 am
by scargill
I wonder if any of your chaps know how to introduce a delay... I have an Arduino client - no matter what I do with it I need a 50us delay between it receiving the first byte and replying in the second - but I don't want to do it as two completely separate transactions each with their own SS sequence... I want to drop SS - do the first byte transfer - wait 50us - do the second transfer - bring SS back up... is that possible??

Re: Exploring the SPI Master interface

PostPosted: Mon Aug 22, 2016 6:11 am
by Noel
I have just done this with a NodeMCU board and can verify that it works.

when configured as HSPICS I think it works as an input to select the ESP as a SPI slave. In most cases this is not required as the ESP will be the master. So It's good to know it can be configured as a digital output even if the other HSPI pins are in use.