- Tue Sep 16, 2014 9:13 am
#643
I'm looking at the SPI Slave mode for this device. Faster host communications and a common bus (SPI) with other popular wifi modules are my primary reasons for looking at this mode instead of the UART mode.
From the ESP8266 design guide (and also the reference documentation for the older ESP8089) it looks like the following is the correct connection for SPI Slave:
It also looks like pin 19 should be tied low through a pull-down resistor (1k) and pin 18 should be left unconnected. There is also some strapping needed to enable SPI slave mode at bootup/etc. It looks like pin 13 (TDO) should be pulled high to select this mode at reset.
The ESP8266 design guide also mentions HSPI connections which are mux'd with the JTAG pins. At this point I'm not sure if it means "Host SPI" mode (where the ESP8266 is a SPI Master to some downstream device) or something entirely different. Does anyone have any information on this?
Does anyone have any protocol/register level data on the SPI slave mode, either for the ESP8266 or older ESP8089?
From the ESP8266 design guide (and also the reference documentation for the older ESP8089) it looks like the following is the correct connection for SPI Slave:
- Pin 7 - CS#
- Pin 20 - MOSI
- Pin 22 - MISO
- Pin 21 - SCK
It also looks like pin 19 should be tied low through a pull-down resistor (1k) and pin 18 should be left unconnected. There is also some strapping needed to enable SPI slave mode at bootup/etc. It looks like pin 13 (TDO) should be pulled high to select this mode at reset.
The ESP8266 design guide also mentions HSPI connections which are mux'd with the JTAG pins. At this point I'm not sure if it means "Host SPI" mode (where the ESP8266 is a SPI Master to some downstream device) or something entirely different. Does anyone have any information on this?
Does anyone have any protocol/register level data on the SPI slave mode, either for the ESP8266 or older ESP8089?
