ESPUSB - Chat about the software components

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By cnlohr
#53117 It is frustrating since I was able to get everything with no extra wait states or anything purring along when it comes to sending data. <3 the fact that you can keep issuing instructions, happy as a clam after you initialize a write. But, reading, man... So sad reading.

1) Can you speak to if the '32 will have the same limitation?

2) Any word on if the DMA is plumbed up any interesting / possibly useful way? So far, I've only ever seen I2S DMA stuff, surely it's used elsewhere?
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By RichardS
#53156
cnlohr wrote:1) Can you speak to if the '32 will have the same limitation?


Guess we need to wait and see, I expect there must still be hidden information coming on a fast read, it seems very strange to me that this would happen, its not a 1 or 2 extra cycles.... its crazy extra..... does not compute :-)

RichardS
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By RichardS
#53498 @cnlohr Any news? Any more insight? What's the next piece of information you need?

RichardS
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By projectgus
#53545
cnlohr wrote:1) Can you speak to if the '32 will have the same limitation?


I don't know for sure. The GPIO subsystem has changed quite a bit, but I don't think anyone had 12Mbit bit-bang reads in mind as a use case (!) so I'm not sure if any of it will make a big difference for this. One big thing which should help is that the peripheral bus with the GPIO subsystem will run at a higher default clock frequency.

Similarly, the ESP32 CPUs now have a 4 entry write buffer which should make bit-banging output at high speed quite flexible. However I don't know if anything relevant changed on the reading side. From the CPU designer & compiler writer's point of view it's a lot more straightforward to assume that your CPU registers have consistent values after each CPU cycle is complete. :)

2) Any word on if the DMA is plumbed up any interesting / possibly useful way? So far, I've only ever seen I2S DMA stuff, surely it's used elsewhere?


This is changing in ways you may find useful - more documentation, more flexibility. The I2S system itself supports more I/O options. I don't think this documentation is coming in the initial hardware documentation release, but it'll be coming soon after it.

Sorry for the lack of specifics, it's pretty crazy busy so haven't had much time to really dig into things.