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By sch0bert
#82953 Hi,

I'm looking to setup my Rx sampling rate up to 24 Mhz in the I2S port but from the formula I found in github, seems to not be possible:

WS = BCLK/ 2 / (16 + I2S_BITS_MOD)

Also, I couldn't find much information about this in the Technical reference manual from ESP8266. In some other sample code, people mention that I2S_CLKM_DIV_NUM value can not be lower than 5 neither I2S_BCK_DIV_NUM be lower than 2 but I can't find the reason about it.

So in concrete what will be the maximum stable sampling rate I can reach?

Thanks in advance
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By davydnorris
#83118 I run at 48KHz and that's stable.

I'm not sure you could get much higher than that, and 24MHz is completely out, for several reasons:
- the PLL clock speed is fixed at 160MHz, so this is the absolute maximum bit rate possible for I2S, and it has to shift 64 bits of information per sample (32bits x 2 channels), so you're already down to 2.5MHz
- on top of this, the calculation you mentioned earlier comes into play so . You are correct about the values of the dividers
- while the I2S bus can operate at this maximum level, you then have DMA transfers into a very small number of buffers in RAM, and then you have to do something with the data. Even at 48KHz there's not a while lot of time to process the buffers before they fill. At 24MHz you'd completely overflow the DMA buffers before ever being able to clear them.