eriksl wrote:This is just by calling rom_i2c_writeReg I guess. So I assume you use the system API function (or direct hardware access) for setting 160 MHz clock to double the PLL CPU clock? Or something else?
As some ranges yield the same frequency, it looks like only some bits are used for PLL/clock divider. I think we should work out which bits are significant and only use these, the other bits may have another function and may be messing up other operation, who knows...
I think 368 MHz already is very good, as the rumours are that the CPU can run up to ~400 Mhz.
I am quit experienced in assembly programming, it's just that it's Z80 and 68000 assembly language . But I do have a document that describes xtensa instructions, so we should be able to figure out what it does. I already read the rom code does some obfuscation by adding and subtracting some "magical" values, bah.
In the end I'd like for us to actually know what I/O addresses are used and them access them directly, without obfuscating rom code. I believe some already had found out some of this.
I found about that on a nosdk8266, here https://github.com/cnlohr/nosdk8266/blob/master/src/nosdk8266.c#L32 Sadly, the trick only works if the speed is 80 MHz
I'm pretty sure that if we can unlock the PLL, we can push the entire system to 520 MHz, the PLL divider would be 2 (1040/2). I really think the silicon in the ESP8266EX is capable of that.
If you have a moment later, please look at this https://github.com/cnlohr/nosdk8266/blob/master/useful/rom/disrom.s#L12272, I was doing some experiments, but I always receive garbage through the UART port.
The two possible ways to go would be to experiment with rom_rfpll_set_freq or to find a way to disconnect the PLL splitter and try to bring everything to 1040MHz although I don't know if the ESP8266EX is capable of handling that speed.