eriksl wrote:I am very curious of your findings.
Do you do anything with the "cpu clock doubler" (i.e. turn it off or on explicitly)? I'd rather have a CPU running at a "high" frequency and the APB at half of it (like it normally does), because then there is more chance that all peripherals will continue to work.
The CacheReadEnable (-Disable) functions have to do with mapping flash memory to IRAM. I am not sure how your knowledge is at this point, forgive me if you already know: there is in total 64 kb IRAM in the ESP8266. 32 kb is used for "iram" code i.e. functions that are not specifically mentioned as to not cache in IRAM. The other 32 kb is used for caching flash memory as the processor cannot execute instructions directly from flash. The CacheReadEnable functions (or CacheReadEnable2 versions) set up this caching. They can "mirror" at most 1 Mbyte of flash memory and you can choose which one, out of four (@ 0 Mb, @ 1 Mb, @ 2 Mb, @ 3 Mb).
I think your code runs in IRAM (I don't know how you build it to an image?), so it shouldn't depend on the flash cache. I don't know why the nonosdsk does something with it anyway?
I use the function
Code: Select all$(ESPTOOL) elf2image $(TARGET_OUT) -o $(TARGET_OUT)-0x00000.bin
the same as in nosdk8266 but for the last esptool.py.
Yes, i do set the overclock bit, so i have a PLL of ~195 MHz and the CPU of ~390 MHz.
Yesterday i made a lot of experiments, but after disable I2S (i find that I2S at such that speed cause troubles) and disable the cache, my code work for a time and then it start generating errors. Maybe was soemthing that i change, but im implemmenting all things again in a new copy of my nosdk8266 fork to merge all tested.
i found this combination: 189/0x00/0x88 (UART divider at 189, this means PLL at 189 MHz, CPU reg 0x00, Charles wrote that this put the CPU at arround 190 MHz and 0x88 on the PLL reg, this put the PLL at arround ~185 MHz)
So, in an hour or so i will start removing all I2S/Cache code and see if it still stable at 346 MHz, if all works for an hour, i will inseert the 390 MHz registers and do a test over all the night.
I remember that yesterday, i ended up with some FLASH reading errors, some printf errors and some error in main (all from disrom.S) so i guess that the ESP8266 start failing at this such speed. we need check rfpll_set_freq, of find in the ROM where is the code that sets the PLL/CPU divider and change it.