eriksl wrote:I am also worried about the max flash frequency (you may be talking about this). Each flash chip type has a maximum clock frequency it can be driven at. Most are quite a bit higher than the SDK code sets it up for (according to esptool that's either 40, 26, 20 or 80 Mhz), I believe iet's 40 Mhz by default but most chips (but not all...) will also run at 80 Mhz. If your change to the PLL also influences the flash clock, it would go up by more than 100%, the flash clock would raise to above 80 Mhz...
So I think the safest approach is to only raise the clock to about 200% (320 Mhz).
I am also very curious which peripherals still work at that frequency and if we even get wifi working, it would be great (but I don't count on it).
If you have a "simple" procedure for me, I could test that too. I'd like to test:
- can we raise the clock speed and then also lower it again to "normal" settings
- what will still work at the raised speed
- if wifi doesn't work, can be make a procedure where wifi is temporarily shut down (there is SDK code for that), clock raised, do the work, clock reset and then enable wifi again. Maybe it even works without temporarily shutting down wifi.
- just as the flash clock is probably influenced by the PLL clock (SPI peripheral), the HSPI peripherical will probably too. I may keep working, but we'd need to adjust the dividers to keep the proper frequency.
I can point you to the name of the ROM functions that start crashing at such that high speed, im very sure that we can push this even further.
As for the WiFi thing, on the I2S code of nosdk8266 project, you can see this line https://github.com/0z4/nosdk8266/blob/master/src/nosdki2s.c#L86
That changes the BBPLL speed, idk what is that PLL or if matters, but is the only reference to other PLL.