Re: Flash Layout and SPIFFS
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Hi Richard -
Thanks for the ideas. I've done some more (preliminary) investigation and discovered one new item. Again, my layout is a 4MB Flash (ESP-12) that's been split in half with the first slot starting at 0x02000 (ROM0) and the second at 0x202000 (ROM1). I have BOOT_BIG_FLASH enabled and can flash one ROM in the upper region and another in the lower region and (manually) switch between them by sending my app an MQTT command instructing it to switch slots.
So, early tests show that I can fairly reliably (minus an occasional time-out) flash ROM1 from ROM0 via the OTA mechanism. However, trying to flash ROM0 from ROM1 *always* results in the lock-up in spi_flash_erase_sector() at sector 2. Does this make sense. Could there be some issue with the 1MB mapping?
I tried to put a ets_print() in my replacement Cache_Read_Enable_New() function but I can never seem to catch it at start-up. However, if I flash two different images into each slot I can *see* that two different images are running when I switch between slots. Can you think of any reason it would be tough for me to catch the ets_printf() in my Cache_Read_Enable_New() override? When should I expect to see it? What's the baudrate when it's shown? Any suggestions there would help. I have looked in my libmain2.a file (that I'm linking against) and it is marked as "(w)eak".
Finally, still no time to investigate SPIFFs in any detail. There is something not quite right there as well.
Thanks for your continual feedback . . . it's been helpful.
Thanks for the ideas. I've done some more (preliminary) investigation and discovered one new item. Again, my layout is a 4MB Flash (ESP-12) that's been split in half with the first slot starting at 0x02000 (ROM0) and the second at 0x202000 (ROM1). I have BOOT_BIG_FLASH enabled and can flash one ROM in the upper region and another in the lower region and (manually) switch between them by sending my app an MQTT command instructing it to switch slots.
So, early tests show that I can fairly reliably (minus an occasional time-out) flash ROM1 from ROM0 via the OTA mechanism. However, trying to flash ROM0 from ROM1 *always* results in the lock-up in spi_flash_erase_sector() at sector 2. Does this make sense. Could there be some issue with the 1MB mapping?
I tried to put a ets_print() in my replacement Cache_Read_Enable_New() function but I can never seem to catch it at start-up. However, if I flash two different images into each slot I can *see* that two different images are running when I switch between slots. Can you think of any reason it would be tough for me to catch the ets_printf() in my Cache_Read_Enable_New() override? When should I expect to see it? What's the baudrate when it's shown? Any suggestions there would help. I have looked in my libmain2.a file (that I'm linking against) and it is marked as "(w)eak".
Finally, still no time to investigate SPIFFs in any detail. There is something not quite right there as well.
Thanks for your continual feedback . . . it's been helpful.