ESP8266 Community Forum

Flash chip is on a dedicated interface. ROM support for 512KB or 4MB chip, 4K or 16K sectors.

There is a second SPI controller. It has three chip selects available.

Do we know some of the chip-level details? Things like

• why are pins 16 (VDD) and 24 (DVDD) unconnected?
• What the different voltage domains (VDDA, VDDD, VDD3P3, VDD_RTC, VDDPST and DVDD) are?
• The function of pin 6 (TOUT)?
• The function of pin 7 (XPD_DCDC)?

My educated guesses for the rails:

• VDDA/VDDD for analog and digital supply domains
• VDD_RTC a low-power rail that only powers an internal RTC (but there's no external 32kHz crystal)
• VDD3P3 an input rail for an internal LDO/DCDC converter
• VDDPST no idea, seems to be an I/O supply rail maybe
• DVDD and maybe VDD are perhaps outputs from the internal LDO

The pin XPD_DCDC is perhaps an enable line for some internal regulator.

edit 20140916: it appears that pin 16 and 24 are GPIO now (GPIO4 and 5, respectively), and that XPD_DCDC is a power down pin which may disable the transmitter (X=transmit) without requiring the chip to "reboot" when coming out of power down. TDO is also known as GPIO15 and determines master/slave boot mode.

It'd be *really* nice to get some information on the slave boot mode and whether you can communicate with the device via SPI instead of UART.

Have a look....thks

Have you seen this document on the 106 micro?
http://ip.cadence.com/uploads/pdf/106Micro.pdf