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Re: What we know so far

PostPosted: Sat Aug 30, 2014 2:10 pm
by jonsmirl
The module is available in four configurations, scroll down and there is a photo showing all four.
http://item.taobao.com/item.htm?spm=a1z ... 0328222213
They cost in the $3.50-4.00 range.

Bare chip is $2.00
http://item.taobao.com/item.htm?spm=201 ... 0551765526

Re: What we know so far

PostPosted: Sun Aug 31, 2014 4:32 am
by hackrid
some of the pins are used to configure the chip during bootup.

Re: What we know so far

PostPosted: Sun Aug 31, 2014 4:49 pm
by Squonk
hackrid wrote:some of the pins are used to configure the chip during bootup.

From the cited document, the available bootstraps are:
  • GPIO15=1 => SDCard startup
  • GPIO15=0 + GPIO2=1 + GPIO0=0 => UART download
  • GPIO15=0 + GPIO2=1 + GPIO0=1 => Flash startup

Re: What we know so far

PostPosted: Sun Aug 31, 2014 5:03 pm
by Squonk
Some information regarding the LX106 CPU are available in the "Tensilica Diamond Standard Controllers Data Book":
The Tensilica Diamond Standard Controllers are a family of 32-bit microprocessor cores
based on Tensilica’s Xtensa Instruction Set Architecture (ISA). Unlike the Xtensa config-
urable processors, however, the cores are fixed processors with little configurability and
no extensibility. They are designed for easy adoption and can quickly be integrated into
system-on-chip (SOC) designs.
There are five general purpose controllers and applications processors as listed in the
following table.

Table 1–1. Diamond Standard Controllers Lineup

Diamond Core
RISC System Control
106Micro Smallest 32-bit licensable controller. Cache-less and optimized for ultra-low power and low area
108Mini Compact, cacheless, optimized for low gate counts
212GP Mid-performance with I and D caches and DSP instructions

233L Adds Linux-compatible MMU to 212GP
570T Extremely high-performance, 3-issue static superscalar processor, with additional I/O

All Diamond Series processors implement the core Tensilica Xtensa ISA instructions
(see Section 2.5 “Instruction Set Summary”), which are a set of 24-bit instructions tar-
geted to a wide range of embedded applications. Most common instructions have a
16-bit narrow encoding as well, and the Diamond Series architecture allows modeless
switching between 16-/24-bit instructions. Consequently, the Diamond Series proces-
sors achieve one of the highest code densities among all 32-bit RISC processors.


Among the controllers, the Diamond 106Micro and 108Mini are designed for lowest area
and lowest power. These cache-less controllers are ideal for tasks ranging from interrupt
managers, finite state machine implementations to MP3 (audio) decode, printer control,
motor control, and automotive controllers. The local, tightly-coupled memories on these
two processors can be used to store performance-sensitive code and data, for example,
to achieve high performance on interrupt handlers. Whereas the Diamond 106Micro has
an iterative, multi-cycle (non-pipelined) multiplier, the Diamond 108Mini has a full 32x32
multiplier and a divider and hence, gives higher performance on algorithms with higher
DSP content (such as audio decode or imaging). The 106Micro core uses a non-win-
dowed 16-entry AR register file that is ideal for fast context switching and potentially
does better on applications that have very deeply nested function calls, since it never
throws a windowing exception. Applications running on the other processors can choose
to use this non-windowing mode if desired.

From the above, it looks like our lx106 CPU is the smallest, fixed, cache-less version of the Xtensa CPU with multi-cycle multiplier, no hardware divider and only 16 (not 32) registers, 15 IRQs instead of 22.