Chat freely about anything...

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By rudy
#82645 It is better, but I don't have time to go through it in detail. But I will comment about one thing.

My guess is that you are using an auto-router? If so then it explains why it is routed stupidly. And what I mean by that is the lack of space between adjacent traces and pads.

Bad auto-routers will place traces with the minimum allowed spacing even though there is lots of room to provide generous spacing between traces/pads/copper. I look at the routing and I cringe.

Look at the traces above reference R23. There is plenty of room to put space between those traces and the pads. That is just one example. There are lots that problem on the board.

For many years my minimum allowable clearance was 12 mills. I have only changed that down in the last few years when I have had to use higher density surface mount parts. But when I can I always allow generous spacing.

Why do you need space? To reduce the likelihood of foil shorts between traces, and to reduce adjacent noise coupling onto traces.
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By Pablo2048
#82651 Rudy is right - it is better, but still not good. Reasons:
1. C4,C5 are still too far from ESP power pins
2. power traces are thin - make them wider - it seems like trace to GPIO12 is wider than trace to VCC.
3. GPIO12 is still unprotected
4. You have added C2 - I suggest to add EMI filter between C2 and C1 in + path
And one suggestion about routing:
Use preferred direction on side - for example horizontal on top and vertical on bottom. Then route your traces and try to follow preferred directions. After you have routed all the traces you can start optimizing them (removing vias, ...). As last thing you have to fill copper pour areas and make final touches.
Maybe you can redraw your schematic also to make it more readable - there is no need to interconnect every GND pin together - just use GND symbol. U1 has to be rotated from this weird orientation. SW3 and SW4 are too far to follow the traces and BTW you are missing junction point in SW3
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By BillM
#82677 What exactly is wrong with U1 ? Right side is for the mosfets and left sides are inputs.

About the EMI filter, for what characteristics should I choose it ?
Also I did a big mistake with C1 and C2, they were connected to output instead of GND :lol:

I have also added 1k resistor with 10nF capacitor. Is this good values for max input frequency of 250Hz ?

Ok, here is what I did.