Discuss here different C compiler set ups, and compiling executables for the ESP8266

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By tschmid
#41678 If anybody is interested, I took the different openocd projects that I could find and forward ported them to mainline OpenOCD. My patch is under review here, in case you want to try it out:


I tested it with a Sparkfun ESP8266 Thing. I can step, next, and set breakpoints. Image load doesn't work for the external spi flash though.
User avatar
By tegila
#41715 I follow this thread by many months and have successfully connected my USB Bus Blaster V4.1, UM232H-B and Flyswatter2 to ESP12 and to NodeMCU(after removal of R6[GPIO15]).

But just after connected i'm getting stuck trying to change the $pc or jump to any address.
The processor keep cycling between 0x4000118c-0x40001189 forever.

I have tried 3 version of OpenOCD(projectgus, sysprogs and the last one that was submitted to openocd git repositories), also I give a try on Linux, OSX and Windows(sysprogs+VS).

I'm really interested in this project as I can't even imagine a professional or educational development without a good view of what is happening inside the app.

This is a view of where i'm stuck:
Code: Select all(gdb) mon reset halt
TAP esp8266.cpu does not have IDCODE
xtensa_poll: DOSR has set InOCDMode without the Exception flag. Unexpected. DOSR=0x04
esp8266.cpu: target state: halted
halted: PC: 0x4000118c
debug cause: 0x20
xtensa_deassert_reset: 'reset halt' is not supported for Xtensa. Have halted some time after resetting (not the same thing!)
(gdb) load app.out
Loading section .data, size 0xa4c lma 0x3ffe8000
Loading section .rodata, size 0xda8 lma 0x3ffe8a50
Loading section .text, size 0x5bfe lma 0x40100000
Loading section .irom0.text, size 0x2137c lma 0x40240000
Start address 0x40100004, load size 165742
Transfer rate: 27 KB/sec, 12749 bytes/write.
(gdb) set $pc=0x40100004
(gdb) info frame
Stack level 0, frame at 0xf00d020c:
 pc = 0x4000118c; saved pc 0x40260fbc
 called by frame at 0xf00d020c
 Arglist at 0xf00d020c, args:
 Locals at 0xf00d020c, Previous frame's sp is 0xf00d020c
(gdb) stepi
0x40005668 in ?? ()
(gdb) stepi
0x4000566b in ?? ()
(gdb) stepi
0x4000566d in ?? ()
(gdb) stepi
0x4000118f in ?? ()
(gdb) stepi
0x40001189 in ?? ()
(gdb) stepi
xtensa_step: Timed out waiting for target to finish stepping.

[Remote target] #1 stopped.
0x4000118c in ?? ()

Sorry if my doubt is too simple, as I read this can be happening because of wdt but `set *0x60000900=0` not solved the problem.
User avatar
By Zachary Comstock
#53172 Has anyone had any success with this version of openocd or the one from sysprogs? I keep getting this error at startup:

Code: Select allOpen On-Chip Debugger 0.9.0 (2016-08-09-00:01)
Licensed under GNU GPL v2
For bug reports, read
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain connect_deassert_srst
adapter speed: 1000 kHz
   TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
 0 esp8266.cpu            Y     0x00000000 0x00000000     5 0x01  0x1f
Info : clock speed 1000 kHz
Error: JTAG scan chain interrogation failed: all zeroes
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway...
Error: esp8266.cpu: IR capture error; saw 0x00 not 0x01

Although it seems like OpenOCD can't connect, I can actually set and read memory from GDB. Breakpoints and stepping don't work though.

I'm using FT2232 dev board as JTAG adapter. openocd.cfg:

Code: Select allset _CHIPNAME esp8266

interface ftdi

ftdi_vid_pid 0x0403 0x6010
ftdi_serial "ATAF31C"

ftdi_layout_init 0x0000 0x003b
ftdi_layout_signal nTRST -data 0x0010 -noe 0x0010
ftdi_layout_signal nSRST -noe 0x0020
ftdi_channel 0

transport select jtag
reset_config srst_only
adapter_khz 1000

jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f

target create $_TARGETNAME xtensa -endian little -chain-position $_TARGETNAME

# esp8266 seems to have a quirk where the JTAG hardware doesn't work
# at all for ~20ms after RST is released. We do a custom reset to
# avoid JTAG layer errors
proc init_reset {mode} {
    # assert both resets (SRST/TRST not a clear division on esp8266 anyhow)
    jtag_reset 1 1
    sleep 30
    jtag_reset 0 0

   # wait for debug port to wake up
   sleep 30

   # validate scanchain
   jtag arp_init

# Disable system watchdog when halted to avoid unexpected resets
$_TARGETNAME configure -event halted {

proc stop_wdt { } {
   mww 0x60000900 0

As a side note, is there any information about lx106 JTAG interface available? Like IR commands? I'd like to check out what's wrong with a logic analyzer.

EDIT: found OCD docs, too bad there are many configuration options affecting JTAG.