ESP8266 Community Forum

- Thu May 28, 2015 5:12 am #18722

Seems pointless to me having cache size of same size as flash.
Newer boards have more flash.
Is that usable for a bigger "rom" segment >32k getting cached by 32k iram segmant?

FLASH is mapped at the 0x40200000...0x4027ffff (standard 512KB). AFAIK the whole 512KB are cached by the FLASH cache, but tests show that there's only 32KB of that cache. Looks like it's that memory that can be mapped at 0x40108000...0x4010ffff is used as the FLASH cache when it's enabled.

- Thu May 28, 2015 5:39 am #18723

The following thing disables high 32KB of IRAM (ROM code in the range 4000476b...4000477a):
*(uint32_t*)0x3ff00024 |= 0x18;

To be more precise it's the bit 0x10.
This is done as one of the last steps in the Cache_Read_Enable.
Clearing that bit enables high 32KB of IRAM.

Even funnier: bit 0x10 controls mapping of lower 16KB in the range 0x40108000..0x4010bfff and bit 0x8 controls higher 16KB, 0x4010c000..0x4010ffff.

- Thu May 28, 2015 6:57 am #18726

Seems pointless to me having cache size of same size as flash.
Newer boards have more flash.
Is that usable for a bigger "rom" segment >32k getting cached by 32k iram segmant?

FLASH is mapped at the 0x40200000...0x4027ffff (standard 512KB). AFAIK the whole 512KB are cached by the FLASH cache, but tests show that there's only 32KB of that cache. Looks like it's that memory that can be mapped at 0x40108000...0x4010ffff is used as the FLASH cache when it's enabled.

Sounds reasonable.

Get your modules here:

https://www.banggood.com/custlink/KvGGhGF4wG

- Sat Jun 06, 2015 4:34 am #19629 Thanks for the responses. I haven't managed to look into anything yet unfortunately.
I have marked all of the functions already with the ICACHE_FLASH_ATTR macro, I suspect though that as it is all interrupt driven at the moment that it is being ignored. I'll have to investigate the map and see whether I note something that needn't be there