ESP8266 Community Forum

- Mon Apr 15, 2019 6:20 pm #81818 I have generated the cross ref actually, and have done a little digging - seems to be uart code using it, so I'll go in and check the uart driver code I'm using.

I've done a lot with I2S and it was my immediate thought because you use DMA to transfer data between the I2S device and the chip and there's an ISR involved - first step inside the ISR you have to clear the DMA interrupt.

I'll dig some more and let you know

- Tue Apr 16, 2019 4:03 am #81823 So I ended up removing libhal from the library link list and everything linked fine. Something has changed and the HAL appears to be no longer required for some reason.

- Tue Apr 16, 2019 12:49 pm #81835

So I ended up removing libhal from the library link list and everything linked fine. Something has changed and the HAL appears to be no longer required for some reason.

Yeah, like I said, the complete HAL is in ROM and has it's entries now "PROVIDE"d in the load script. If you remove these there, the link will fail.

- Tue Apr 16, 2019 12:55 pm #81836

I have generated the cross ref actually, and have done a little digging - seems to be uart code using it, so I'll go in and check the uart driver code I'm using.

Are you using own code for the UART or that in driverlib? Again the code from Espressif is horrible. I'd really advise to do it yourself. All relevant data of the UART is known now.

I've done a lot with I2S and it was my immediate thought because you use DMA to transfer data between the I2S device and the chip and there's an ISR involved - first step inside the ISR you have to clear the DMA interrupt.

I'll dig some more and let you know

Masking, unmasking and clearing of interrupts can all be done without HAL code.

There is some weird code in ROM to be called for enabling the I2S module (called i2c_something, notice the misnomer here!). If I really start to be seriously bored, I am going to reverse engineer that code and find out what registers are actually involved for I2S, including the PLL registers, which would allow us to run the CPU core at up to 320 MHz, the hardware can do it, it's designed for it. The only thing is that the WLAN module can't work at that speed. I'd be interested in a scenario where the CPU is run at higher speeds for short periods, while doing complex work and then drop back to 160 Mhz mostly for operating the WLAN module.