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By vitorrossi
martinayotte wrote:
rudy wrote:I don't know why you are getting those transitions during the high time.

It is know that GPIO0 produce some clock output during reset, it cannot be avoided :

Ok this explains the signal at boot, I'm glad it is not an issue with my circuit.
I will attempt to add a low pass filter to prevent the clock output from being sent to the darlington transistor, I this should solve the problem. I will post once I've tried it. Thank you.

Rudy, could you please help me understand your suggestion? I was a bit confused with the terminology, where would the GPIO and the Darlington transistor from my circuit connect to the circuit you provided?