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By vitorrossi
martinayotte wrote:
rudy wrote:I don't know why you are getting those transitions during the high time.

It is know that GPIO0 produce some clock output during reset, it cannot be avoided :

Ok this explains the signal at boot, I'm glad it is not an issue with my circuit.
I will attempt to add a low pass filter to prevent the clock output from being sent to the darlington transistor, I this should solve the problem. I will post once I've tried it. Thank you.

Rudy, could you please help me understand your suggestion? I was a bit confused with the terminology, where would the GPIO and the Darlington transistor from my circuit connect to the circuit you provided?
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By vitorrossi
#82845 Apologies it took me sometime to write back, I did not have time to play around with this until now.
Rudy, I researched your suggestion and ended up understanding what you meant, I just didn't have the background to get it the first time.
I tested both the NPN and PNP circuits and both worked, and I understand why the PNP is preferred in this case.
I added a capacitor after the collector-resistor on the PNP to create a low pass filter, since the 3.3V clock output was still operating the solenoid. The addition of the capacitor solves this issue.
Below I have the final schematic of the circuit, works well on the breadboard and hopefully will work well once I solder everything onto a perfboard.
Thank you again to both of you for pointing me in the right direction