I guess I have freed up over 32 kbytes by doing that. If I wouldn't be doing this, development of my image would have ceased years ago
Having said that, Espressif has distributed a piece of example code, where mp3 is decoded into audio (PWM and I2S) and it requires more memory than DRAM available on the ESP8266. They have a suggestion where SPI RAM (not flash) is added.
The RAM chip is soldered piggy back to the SPI flash chip, leaving only the CS line, which is to be connected to GPIO0 IIRC.
If I understand it all correctly, the trick is like this:
- the SPI/HSPI interface is programmed in "combined" mode, where both use the same pins (so you still have all GPIO's available, minus one)
- because for RAM access the HSPI interface is used, it doesn't interfere (greatly) with the SPI interface, used for flash access
- for RAM access, the GPIO0 pin is used as CS; when this is asserted, the SPI RAM will react and the flash chip will remain sleeping, because it's CS is not asserted
- for flash access, the reverse happens
- you can read/write arrays of 64 bytes at a time, not really random access, for but for large chunk data style memory, it may be very well be usable
- also no memory-style access possible (like flash)
- I am not sure if the code that access the SPI RAM must be in IRAM (no flash access) or not, but I am going to find out, I ordered some of these chips.
The ESP32 has an interface to SPI RAM similar as to SPI flash, where you can have random access using memory address interface, BUT I've read there are quite a lot of caveats.
The alternative could also be to start using FRAM memory over IC. I've ordered some of these too, so let's see.